完整後設資料紀錄
DC 欄位值語言
dc.contributor.author涂芷菱zh_TW
dc.contributor.author何宜臻zh_TW
dc.contributor.author宋柔穎zh_TW
dc.contributor.author許心縈zh_TW
dc.date114學年度第2學期zh_TW
dc.date.accessioned2026-10-20T05:22:15Z-
dc.date.available2026-10-20T05:22:15Z-
dc.date.submitted2026-10-15
dc.identifier.otherD1323091、D1358274、D1388276、D1323031zh_TW
dc.identifier.urihttp://dspace.fcu.edu.tw/handle/2376/5245-
dc.description.abstract中文摘要 本專題旨在運用 Verilog 硬體描述語言與 FPGA 開發板(Altera DE0)控制技術,開發一套支援單人與多人的 21 點(Blackjack)撲克牌遊戲系統,以模擬真實賭場遊戲情境,並提升數位邏輯與軟硬體整合的實作能力。系統核心功能涵蓋遊戲模式選擇、虛擬籌碼下注、發牌與補牌機制、ACE 點數智慧轉換、多人回合切換以及自動結算模組,期望藉由完整的功能設計提升玩家遊戲體驗與硬體操作互動性。 在系統設計過程中,以 top_g21 為頂層模組建立完整的系統架構,並將功能細分為主控邏輯(g21)、按鍵防彈跳(btn_debounce)、七段顯示器輸出(seg7)以及數值解碼(BCD)等次模組。核心邏輯主要運用有限狀態機(FSM)進行流程控制,確保遊戲從模式選擇、下注到洗牌、發牌及結果顯示皆能維持順暢的狀態流轉;底層則著重於特定機制的實現,包含利用線性反饋移位暫存器(LFSR)生成偽隨機數進行洗牌,以及處理莊家小於 17 點自動補牌等複雜遊戲規則。同時,透過硬體模組化設計方式,使各子系統能夠彼此協作並具備擴充性,以符合後續硬體功能強化的需求。 專題成果展示出一個可於實體 DE0 開發板上完整運作的 21 點遊戲硬體系統,玩家可透過實體按鍵進行下注或換人等動作,並藉由顯示器即時掌握點數、籌碼餘額與單局勝負結果。整體而言,本系統成功整合實現了邏輯齊全、硬體介面清晰與操作流暢的特點,並具備未來延伸的潛力,包含視覺化介面(VGA 輸出)升級、進階賭場規則實作以及音效系統整合等。zh_TW
dc.description.abstractAbstract This project aims to utilize the Verilog hardware description language and FPGA development board (Altera DE0) control technologies to develop a Blackjack card game system supporting both single-player and multiplayer modes. The goal is to simulate a real casino gaming scenario and enhance practical skills in digital logic and hardware-software integration. The core functions of the system cover game mode selection, virtual chip betting, dealing and drawing mechanisms, smart ACE point conversion, multiplayer turn switching, and an automatic settlement module. Through comprehensive functional design, we expect to improve the player's gaming experience and hardware interaction. During the system design process, a complete system architecture was established using top_g21 as the top-level module, with functionalities subdivided into submodules such as the main control logic (g21), button debouncing (btn_debounce), seven-segment display output (seg7), and numerical decoding (BCD). The core logic primarily employs a Finite State Machine (FSM) for process control, ensuring smooth state transitions throughout the game—from mode selection and betting to shuffling, dealing, and result display. The underlying design focuses on the implementation of specific mechanisms, including the use of a Linear Feedback Shift Register (LFSR) to generate pseudo-random numbers for shuffling, as well as handling complex game rules like the automatic banker draw when points are under 17. Simultaneously, the hardware modular design approach allows the subsystems to collaborate and possess scalability, meeting the needs for future hardware functional enhancements. The project results demonstrate a Blackjack hardware system that operates fully on the physical DE0 development board. Players can perform actions such as betting or switching turns via physical buttons, and use the displays to instantly monitor point totals, chip balances, and single-round match results. Overall, this system successfully integrates and achieves comprehensive logic, clear hardware interfaces, and smooth operations, while also possessing potential for future extensions, including visual interface (VGA output) upgrades, advanced casino rule implementations, and sound system integration.zh_TW
dc.description.tableofcontents目 次 一、設計目的............................................................................................. 6 二、I/O (input/output) ............................................................................ 6 三、系統架構圖......................................................................................... 7 四、Finite State Machine (FSM)............................................................ 8 五、專題功能簡介.................................................................................... 8 1. 遊戲模式選擇(單人/多人同樂)................................................. 8 2. 虛擬籌碼與下注系統.................................................................... 8 3. 雙倍下注功能(加碼機制) ...................................................... 8 4. 發牌與補牌機制 .......................................................................... 9 5. ACE 點數智慧轉換 .................................................................... 9 6. 多人回合切換管理 ...................................................................... 9 7. 自動結算與派彩系統 .................................................................. 9 8. 即時戰況顯示面板........................................................................ 9 六、未來展望........................................................................................... 9 七、結論.................................................................................................. 10 八、參考文獻.......................................................................................... 10zh_TW
dc.format.extent10p.zh_TW
dc.language.isozhzh_TW
dc.rightsopenbrowsezh_TW
dc.subject21 點zh_TW
dc.subjectFPGA (Altera DE0)zh_TW
dc.subjectVerilog 硬體描述語言zh_TW
dc.subject有限狀態機 (FSM)zh_TW
dc.subject隨機數生成 (LFSR)zh_TW
dc.subjectBlackjackzh_TW
dc.subjectFPGA (Altera DE0)zh_TW
dc.subjectVerilog Hardware Description Languagezh_TW
dc.subjectFinite State Machine (FSM)zh_TW
dc.subjectRandom Number Generation (LFSR)zh_TW
dc.title微處理機實習-21 點zh_TW
dc.title.alternativeMicroprocessor Lab: Blackjackzh_TW
dc.typeUndergraReportzh_TW
dc.description.course微處理機實習zh_TW
dc.contributor.department電子工程學系, 資訊電機學院zh_TW
dc.description.instructor楊, 鎮安
dc.description.programme電子工程學系, 資訊電機學院zh_TW
分類:資電114學年度

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