Low-Power Sequential MRU Cache Based on Valid-Bit Pre-Decision

Abstract

The conventional sequential MRU cache has longer access time because the MRU information must be fetched from the MRU table before accessing the memory banks of cache, and incurs larger power consumption due to multiple accesses of memory banks. In this paper, focusing on the sequential MRU cache with sub-block placement, we propose an MRU cache scheme that separates the valid bits from data memory and uses these valid bits to pre-decide reducing the unnecessary access number of memory banks. By this approach, the probability of the front hits is thus increased, and it significantly helps in improving the average access time and average energy dissipation of the sequential MRU cache without valid-bit pre-decision search especially for large associativity and small sub-block size.