| 題名: | Reconfigurable Processor Core Design for Network-on-a-Chip | 
| 作者: | Chen, Shih-Lun Jou, Jer-Min Sun, Chien-Ming Wu, Yuan-Chin Yang, Haoi Su, Hong-Yi | 
| 關鍵字: | Reconfigurable NoC | 
| 期刊名/會議名稱: | 2004 ICS會議 | 
| 摘要: | Today, the cost of mask in SoC is increasing rapidly. Designing a complex system-ona- chip (SoC) confronts many challenges. Networkson- a-chip (NoC) is a new architectural template, which helps to meet many of these challenges and enables fast time to market for new designs. How to transfer high-speed and macro data for computing and reusing macro transistors proves to be more and more important in the area of IC design. The reconfigurable processor turns into a research focus by many SoC researchers in the world. This paper offers a new powerful, flexible, and reusable reconfigurable processor for NoC, which will process no matter general or special purpose applications with high performance. It could handle software well like a superscalar CPU and process some special applications with macro data efficiently like an ASIC. Our results show that the reconfigurable processor design greatly improves the performance than traditional processor design. | 
| 日期: | 2006-10-16T05:57:31Z | 
| 分類: | 2004年 ICS 國際計算機會議 | 
文件中的檔案:
| 檔案 | 描述 | 大小 | 格式 | |
|---|---|---|---|---|
| ce07ics002004000165.pdf | 400.22 kB | Adobe PDF | 檢視/開啟 | 
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