An Efficient Variable Partitioning and Scheduling Algorithm for DSP with Multiple Memory Modules

Abstract

Multiple on-chip memory modules are attractive to many DSP applications. This architectural feature supports higher memory bandwidth by executing multiple data memory accesses in parallel. However, the performance gain in this architecture strongly depends on the variable partitioning and scheduling method. In this paper, we propose an efficient rotation scheduling with parallelization (RSP), which is extended from our previous studies. RSP includes a simple mechanism to partition variables, and uses rotation scheduling and unimodular transformations to generate effective results. We also design an analytic model to analysis preliminary performances. Based on our analyses, RSP can obtain quite effective results compared with related methods.