The FPGA Design of the Scan Conversion for Multimedia

Abstract

Image scaling is important in conversion between different formats such as VGA, NTSC and HDTV. As an application, we consider a scan formats, such as a VGA mode into 720p as a target signal format. In this paper proposes the design of a scan converter based on propose adaptive cubic convolution (ACC), which was modeled in verilog and implemented with an FPGA chip. The algorithm (ACC) exhibits of information loss when compared with the traditional interpolation algorithms, particularly in the edge regions. To realize the chip of this design, we use verilog, Xilinx tool and Synopsys library to design and simulate. We use FPGA(XC2V 1000 0.18μm CMOS process) to implement it. The gate count is 825,186. The operating clock rate is 25MHz, 50MHz and 75 MHz, with embedded memory requirement of 16kB.