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dc.contributor.authorWang, Chua-Chin
dc.contributor.authorTseng, Yih-Long
dc.contributor.authorChen, Chi-Wen
dc.date.accessioned2009-08-23T04:47:45Z
dc.date.accessioned2020-05-29T06:17:24Z-
dc.date.available2009-08-23T04:47:45Z
dc.date.available2020-05-29T06:17:24Z-
dc.date.issued2006-10-18T10:56:21Z
dc.date.submitted2001-12-20
dc.identifier.urihttp://dspace.fcu.edu.tw/handle/2377/1946-
dc.description.abstractThe rapidly improved performance of latest CPUs introduces higher clock rates for peripheral devices. Moreover, DDR(double data rate)has been one of the most important methods to increase the throughput of a system, e.g., SDRAM. The edges of the reference clock, thus, become deadly important to these high-speed and high-clock applications. In this paper, we present a pulse generator circuit to generate pulses corresponding to the rise edge and fall edge of a given clock, respectively, without any phase shift and delay. These pulse trains can be used to synchronize the peripherals. The noise rejection is also proved when the given clock is coupled with a 10\% noise. The proposed circuit can be applied to other clock rates beyond 133 MHz as long as the sizes of the delay elements are properly tuned.
dc.description.sponsorship中國文化大學,台北市
dc.format.extent10p.
dc.format.extent286882 bytes
dc.format.mimetypeapplication/pdf
dc.language.isozh_TW
dc.relation.ispartofseries2001 NCS會議
dc.subjectsynchronous devices
dc.subjectDDR
dc.subjectdouble data rate
dc.subjectclock generation
dc.subjectphase shift
dc.subjectdelay cancellation
dc.subject.otherVLSI system design
dc.titleRobust Reference Clock Generator Design for DDR Synchronous Devices
分類:2001年 NCS 全國計算機會議

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