Systematic Array Processors Design for Fraction-Free Algorithm

Abstract

The design of systolic array processors for solving linear systems of equations using fraction-free Gaussian elimination method is presented. The design is based on a formal approach which constructs a family of planar array processors systematically. These array processors are synthesized and analyzed. It is shown that some array processors are optimal in the framework of linear allocation of computations and in terms of number of processing elements, number of input/output ports, time of processing, and data pipelining period.