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dc.contributor.authorYang, Chao-Tung
dc.contributor.authorTseng, Shian-Shyong
dc.contributor.authorFann, Yun-Woei
dc.contributor.authorHsieh, Ming-Huei
dc.date.accessioned2009-06-02T06:18:54Z
dc.date.accessioned2020-05-25T06:38:34Z-
dc.date.available2009-06-02T06:18:54Z
dc.date.available2020-05-25T06:38:34Z-
dc.date.issued2006-10-27T02:56:35Z
dc.date.submitted2000-12-08
dc.identifier.urihttp://dspace.lib.fcu.edu.tw/handle/2377/2656-
dc.description.abstractAs we know, the execution efficiency of a loop can be enhanced if the loop is executed in parallel or partially parallel, like a DOALL or DOACROSS loop. This paper also reports on a practical parallel loop detector (PPD) that is implemented in PFPC on finding the parallelism in loops. The PPD can extract the potential DOALL and DOACROSS loops in a program by verifying array subscripts. In addition, a new model by using knowledge-based approach is proposed to exploit more loop parallelisms in this paper. The knowledge-based approach integrates existing loop transformations and loop scheduling algorithms to make good use of their ability to extract loop parallelisms. Two rule-based systems, called the KPLTan d IPLS, are then developed using repertory grid analysis and attribute ordering tables respectively, to construct the knowledge bases. Finally, a runtime technique based on inspector/executor scheme is proposed in this paper for finding available parallelism on loops. Our inspector can determine the wavefronts of a loop with any complex indirected array indexing pattern by building a DEF-USE table. Experimental results show that the new method can handle any complex data dependence pattern that cannot be handled by the previous research.
dc.description.sponsorship中正大學,嘉義縣
dc.format.extent8p.
dc.format.extent248058 bytes
dc.format.mimetypeapplication/pdf
dc.language.isozh_TW
dc.relation.ispartofseries2000 ICS會議
dc.subject.otherCompilation and Scheduling
dc.titlePFPC: An Infrastructure for Research on Parallelizing Compilers
分類:2000年 ICS 國際計算機會議

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