A 1.25 GHz 8-bit Tree-Structured Carry Lookahead Adder

Abstract

By modifying the so-called all-N-transistor (ANT) design, several small but novel cells are proposed which can rapidly compute the required generate and propagate function, respectively. We utilize these cells to design a 8-bit tree-structured carry look ahead adder (CLA). The 8-bit CLA not only possesses few transistor count, but also occupies small area size. Moreover, the post-layout simulation results given by TimeMill show that the clock used in this 8-bit CLA can run up to 1.25GHz The proposed architecture is also easy to be expanded for long data additions.