Improvement for Reducing Latency of Load Instructions

Abstract

Memory system design is one of the most challenging aspects of comput erarchitecture. One of the important challenges in memory system design is the problem of continually lengthening load latency. This paper proposes three methods to eliminate load latency: FAC-like scheme eliminates one cycle of load latency, LTAPB scheme reduces two cycles, and Hybrid scheme combines above two methods benefit from their advantages. We adopt an execution-driven simulator and apply spec95 benchmarks to simulate the results.