A Multilevel Hardware Architecture for Lossless Data Compression Applications

Abstract

In this paper, we propose a new multilevel hardware architecture that combines the features of both Huffman and PDLZW algorithms. In particular, the memory allocation and the data unit of compression is changed from byte, which is used by PDLZW algorithm, to byte stream. In addition, the tree-based dynamic update method used in adaptive Huffman algorithm is changed to an order list for speeding up the compression rate. The resulting architecture shows that it can reach the same compression ratio as adaptive Huffman algorithm but only at the cost of one-half hardware resource. Furthermore, the compressing data rate is one codeword per cycle rather than one bit per cycle.