完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.author | Wang, Shyh-Jye | |
| dc.contributor.author | Lin, Phen-Lan | |
| dc.contributor.author | Provence, John D. | |
| dc.date.accessioned | 2009-08-23T04:39:04Z | |
| dc.date.accessioned | 2020-05-25T06:28:29Z | - |
| dc.date.available | 2009-08-23T04:39:04Z | |
| dc.date.available | 2020-05-25T06:28:29Z | - |
| dc.date.issued | 2006-10-30T01:29:45Z | |
| dc.date.submitted | 1996-12-19 | |
| dc.identifier.uri | http://dspace.lib.fcu.edu.tw/handle/2377/2836 | - |
| dc.description.abstract | A pipelined RISC has been designed to incorporate the branch-skipped feature. Branch instructions are detected in the first stage of the pipeline and branch target instructions are made available early enough to let the RISC skip all branch instructions. The performance of this RISC is significant compared with other RISCs, with or without the branch-skipped feature. | |
| dc.description.sponsorship | 中山大學,高雄市 | |
| dc.format.extent | 5p. | |
| dc.format.extent | 472897 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.language.iso | zh_TW | |
| dc.relation.ispartofseries | 1996 ICS會議 | |
| dc.subject.other | Microarchitecture and Parallelizing Compiler | |
| dc.title | Design and Performance Evaluation of Branch-Skipped Reduced Instruction Set Computers | |
| 分類: | 1996年 ICS 國際計算機會議 | |
文件中的檔案：
| 檔案 | 描述 | 大小 | 格式 | |
|---|---|---|---|---|
| ce07ics001996000206.pdf | 461.81 kB | Adobe PDF | 檢視/開啟 |
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