Transaction-level Error Susceptibility for Bus-based System-on-Chip: From Single-bit to Multi-bit

Abstract

System-on-Chip architectures have traditionally relied upon bus-based interconnect for their communication needs. The increasing bus frequencies and load on the bus calls for focus on reliability issues in such bus-based systems. As technology advances and transistor geometry shrinks, both single-bit and multi-bit error rate increase significantly. The scant research on mulit-bit errors calls for more attention about them. In this paper, we compare the consequences of a single-bit and multi-bit error and provide a detail analysis of a multi-bit error on the bus system during the course of different transactions. Such transaction based analysis helps us to develop an effective prediction methodology to predict the effect of a multi-bit error on any application running on a bus based architecture. We demonstrate that our transaction based prediction scheme works with an average accuracy of 88% over all the benchmarks when compared with the actual simulation results