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dc.contributor.author馬, 永昌 Jr
dc.contributor.author李, 冠侖 Jr
dc.contributor.author郭, 書銘 Jr
dc.date.accessioned2011-03-24T19:56:52Z
dc.date.accessioned2020-05-18T03:24:14Z-
dc.date.available2011-03-24T19:56:52Z
dc.date.available2020-05-18T03:24:14Z-
dc.date.issued2011-03-24T19:56:52Z
dc.date.submitted2009-11-27
dc.identifier.urihttp://dspace.lib.fcu.edu.tw/handle/2377/30072-
dc.description.abstractIn this paper we apply Sentry Tag based filter scheme to the design of branch target buffer (BTB) of branch predictor in modern processors. The filter scheme filtrates unnecessary accesses of branch target buffer to reduce dynamic power consumption. The proposed scheme not only maintains high branch prediction accuracy and thus high pipeline utilization for processors, but also attains considerable power saving. We use Content-Addressable Memory (CAM) to design the filter scheme and utilize HSPICE and CACTI tools to make sure the proposed scheme’s critical path delay of processor instruction fetch of pipeline is not affected. Based on SimpleScalar/Wattch simulators and SPEC2K benchmarks, we show that our scheme can filter up to 85% of branch target buffer accesses, thus reducing the power consumption for branch prediction unit by 16% - 55%, (the power consumption for branch target buffer by 18% - 75%) without compromising prediction accuracy and processor performance.
dc.description.sponsorshipNational Taipei University,Taipei
dc.format.extent12p.
dc.relation.ispartofseriesNCS 2009
dc.subjectLow Power
dc.subjectBranch Target Buffer
dc.subjectFilter Scheme
dc.subjectSentry Table
dc.subject.otherWorkshop on Computer Architectures, Embedded Systems and VLSI/EDA
dc.titleDesign of Low-Power Branch Target Buffer Using Filter Scheme
dc.title.alternative運用過濾器方法之低耗電分支目標緩衝器的設計
分類:2009年 NCS 全國計算機會議

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