完整後設資料紀錄
DC 欄位語言
dc.contributor.authorLin, Ming-Bo Jr
dc.contributor.authorTzeng, Ing-Jang Jr
dc.contributor.authorHsieh, Ming-Chun Jr
dc.date.accessioned2011-03-24T19:57:20Z
dc.date.accessioned2020-05-18T03:24:20Z-
dc.date.available2011-03-24T19:57:20Z
dc.date.available2020-05-18T03:24:20Z-
dc.date.issued2011-03-24T19:57:20Z
dc.date.submitted2009-11-27
dc.identifier.urihttp://dspace.lib.fcu.edu.tw/handle/2377/30078-
dc.description.abstractIn the thesis, a pipelined architecture of AES plus CBC Encryption/Decryption IP (Intellectual Property) is proposed. This architecture implements the AES algorithm, the input data is a sequence of 128 bits and the cipher key is a sequence of 128, 192, or 256 bits. To provide the flexibility of interfacing with common microprocessors, the data bus width can be set to 8, 16, or 32 bits. To apply AES in a variety of applications, four “modes of operation” (ECB, CBC, CFB, and OFB) have been defined in the IP. To reduce the power consumption, the same set of Round Keys will not be generated many times for every data blocks because all of the Round Keys have been generated and stored in RAM by Key 2 Schedule. Obviously, it consumes less power to compute the same set of Round Keys. Compared with the widely used lookup-table architecture, the Euclid’s multiplicative inverse lookup-table architecture used in the thesis may reduce the hardware overhead of the S-box and InvS-box by an amount of 36.45%. The AES plus CBC Encryption/Decryption IP has been implemented and verified with both Xilnx Vertex 400 FPGA and TSMC 0.25 μm cell library. In the FPGA part, it operates at 30 MHz and can achieve a high throughput of 230.4 Mbps. It takes up LUTs of 73% and Block RAM of 80% in FPGA board. In the cell-based part, it operates at 156.25 MHz and can achieve a high throughput of 1200 Mbps. The core occupies the area of 1671.73 μm×1671.73 μm, which is approximately equivalent to 76610 gates, and consumes about 128.4 mW in the typical operating condition.
dc.description.sponsorshipNational Taipei University,Taipei
dc.format.extent12p.
dc.relation.ispartofseriesNCS 2009
dc.subjectAES
dc.subjectRijndael algorithm
dc.subjectEuclid’s algorithm
dc.subjectEBC
dc.subjectCBC
dc.subjectCFB
dc.subjectOFB
dc.subject.otherWorkshop on Computer Architectures, Embedded Systems and VLSI/EDA
dc.titleA VLSI Architecture for AES with CBC mode
dc.title.alternative一個AES內建CBC模式加密與解密之VLSI架構
分類:2009年 NCS 全國計算機會議

文件中的檔案:
檔案 描述 大小格式 
CEV 2-5.pdf1.92 MBAdobe PDF檢視/開啟


在 DSpace 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。