Reducing Test Power by Partial Gating on Scan-Chain Outputs

Abstract

Consuming much power during testing usually destroy integrated circuits or provide wrong test results. Low-power testing methods therefore become very important nowadays. Inserting control gates at the outputs of all or partial flip-flops is a common method to lower down testing power. In this study, we propose a method to reduce power during test by selecting partial flip-flops for inserting control gates. We first consider critical paths in circuits and choose the flip-flops connecting those critical paths be non-scan flip-flops. This can keep the designed speed for the circuits. The other flip-flops are scanned and further analyzed for inserting control gates. For the first-level connected logic gates of the scanned flip-flops, their amounts and controllability of other input lines are calculated with weight numbers. The obtained data are used to determine both the order of being selected and the gate type of inserted control gates. We experiment the method on ISCAS89 benchmark circuits and deal with their test patterns for transition delay faults. The results prove that the method can help achieve both lower average and peak power during testing.