Implementation of Finite Impulse Response Digital Filter Using Partial Reconfigurable FPGA Platform

Abstract

This paper presents a parallel FIR (Finite Impulse Response) filter system design, using PR(Partial Reconfiguration) to change tap of FIR , which can achieve high flexibility, high performance, and shorten the time of configuration. In the present thesis, we use the Verilog HDL within Xilinx ISE 9.2i design tool to complete this architecture. After that, we use FPGA for function simulation and verify computation data. Until simulation result is correct, using Xilinx PlanAhead 9.2 to merge all of the architecture, it generates full configuration circuit file and partial reconfiguration circuit file. Then, to verify by using iMPACT to download full configuration and partial reconfiguration circuit file to FPGA. The results we found, the file size(memory space) on full configuration are 2444KB, on partial reconfiguration are 166KB, the percent are 6.7 %; and the times need (speed) on full configuration are 6sec, on partial reconfiguration are 1sec, the percent are 16.6 %.