A 500MHz, 8-Stage Pipeline RISC Microprocessor Design with Sub-Computing

Abstract

In this paper, we have demonstrated RISC of embedded system design. Under performance and power consumption premise, Instruction Set design, like sub-computing instruction, load and store mask instruction, repeat instruction and delay branch instruction, has many characteristics in increasing instruction Powerful. Sub-Computing processes the simple operation first using a stage in the pipeline, and then using ALU executes the complex operation. It increases 20% performance in Instruction Set. There are 2 critical paths on Architecture. Improving them can increase frequency from 300MHz to 500MHz and pipeline stage will up to 8. Although increasing pipeline stage has the contradictory place with Instruction Set, we are trying to find out the balance point in the architecture. And we propose the best design way in the paper.