Using Essential Inverters for Interconnect Delay Reduction

Abstract

With the fast advance of VLSI process technology, interconnect delay increasingly dominates the circuit performance. Buffer insertion plays a crucial role in dealing with this problem. However, excessive insertion might cause additional problems and counteract its advantages. In this paper, we propose a gate replacement method to extract essential inverters from positive unate gates. The basic idea is to use inverters originally embedded in a design rather than externally added buffers to drive long interconnects. Our experiments show on average up to 27 % reduction in buffer usage together with 4.6% reduction in clock period. The total slack of the first 100 longest paths is improved by 67.1%. The total negative slack is improved by 53.9%. All these are achieved at the expense of on average 3.1% increase in cell area for the large benchmark circuits.