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dc.contributor.authorShieh, Wann-Yun
dc.contributor.authorHsu, Shu-Yi
dc.date.accessioned2009-08-23T04:43:18Z
dc.date.accessioned2020-05-25T06:52:04Z-
dc.date.available2009-08-23T04:43:18Z
dc.date.available2020-05-25T06:52:04Z-
dc.date.issued2007-01-25T06:49:06Z
dc.date.submitted2006-12-04
dc.identifier.urihttp://dspace.lib.fcu.edu.tw/handle/2377/3466-
dc.description.abstractThe multi-banked register file (MBRF) is one of the most effective approaches to resolve the complexity of the monolithic register files. In order to apply the multi-banked register file to a high-end embedded processor, we design the dynamic voltage (DVS) scaling approach for MBRF to satisfy the energy constraints. However, we found that distributed bank-access behavior prevents voltage scaling from identifying when a bank is active or not. To resolve this problem, in this paper, we analyze the access behavior of temporary-values, and change their storage in banks to increase the opportunities of power saving for infrequently-used register banks. We then turn these infrequently-used register banks into lower mode by our proposed DVS circuit. For a MBRF architecture with four banks, simulation results show that, on average, our approach reduces about 19% energy consumption while performance lose can be limitted by less than 2%, compared with the MBRF without DVS.
dc.description.sponsorship元智大學,中壢市
dc.format.extent6p.
dc.format.extent3791945 bytes
dc.format.mimetypeapplication/pdf
dc.language.isozh_TW
dc.relation.ispartofseries2006 ICS會議
dc.subject.otherPower-Aware Architecture Synthesis
dc.titlePower-Aware Register Assignment for Multi-Banked Register Files
分類:2006年 ICS 國際計算機會議

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