完整後設資料紀錄
| DC 欄位 | 值 | 語言 |
|---|---|---|
| dc.contributor.author | Yi, Shu-Chung | |
| dc.contributor.author | Xie, Yu-Zhi | |
| dc.contributor.author | Lin, Yi-Jie | |
| dc.contributor.author | Zhao, Zi-Yi | |
| dc.date.accessioned | 2009-08-23T04:42:39Z | |
| dc.date.accessioned | 2020-05-25T06:53:26Z | - |
| dc.date.available | 2009-08-23T04:42:39Z | |
| dc.date.available | 2020-05-25T06:53:26Z | - |
| dc.date.issued | 2007-01-26T01:23:26Z | |
| dc.date.submitted | 2006-12-04 | |
| dc.identifier.uri | http://dspace.lib.fcu.edu.tw/handle/2377/3479 | - |
| dc.description.abstract | This paper presents the design of ROM-less quadrature Direct Digital Frequency Synthesizer (DDFS) by using trigonometric angle sum formula. The proposed DDFS consists of two adders and two multipliers to generate quadrature outputs. The results are simulated by using 0.35μm CMOS process technology. The spurious-free dynamic range (SFDR) is about 100dB, runs up to 100MHz and consumes 38.8mW at 3.3 V. | |
| dc.description.sponsorship | 元智大學,中壢市 | |
| dc.format.extent | 4p. | |
| dc.format.extent | 3984078 bytes | |
| dc.format.mimetype | application/pdf | |
| dc.language.iso | zh_TW | |
| dc.relation.ispartofseries | 2006 ICS會議 | |
| dc.subject | Direct Digital Frequency Synthesizer | |
| dc.subject | frequency synthesizer | |
| dc.subject | ROM-less | |
| dc.subject.other | Circuit Design | |
| dc.title | A New Architecture of Rom-Less Quadrature Direct Digital Frequency Synthesizer | |
| 分類: | 2006年 ICS 國際計算機會議 | |
文件中的檔案：
| 檔案 | 描述 | 大小 | 格式 | |
|---|---|---|---|---|
| ce07ics002006000029.pdf | 3.89 MB | Adobe PDF | 檢視/開啟 |
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