A High Performance Sequential MRU Cache Using Valid-Bit Pre-Decision Search Algorithm

Abstract

MRU (most recently used) cache is one of the set-associative caches that emphasize implementation of associativity higher than two. However, the access time is increased because the MRU information must be fetched before accessing the sequential MRU cache. In this paper, focusing on the sequential MRU cache with sub-block placement, we propose an MRU cache scheme that separates the valid bits from data memory and uses these valid bits to decide to reduce the unnecessary access number of memory banks. By this approach, the probability of the front hits is thus increased, and it significantly helps in improving the average access time of the sequential MRU cache without valid-bit pre-decision search especially for large associativity and small sub-block size.