Code Compression Architecture for Memory Bandwidth Optimization in Embedded Systems

Abstract

To boost clock rate for performance goals, RISC cores are widely adopted in designing embedded systems. However the fixed-length instruction sets of RISC architecture have poor code density thus burden memory bus contention. For an embedded system, it’s common to have multiple bus masters connected to system bus and contend for bandwidth. This paper proposes code compression architecture to mitigate such conditions. The scheme we posed can effectively alleviate the stress on bus contention by reducing traffic due to program fetch. Meanwhile, the instruction cache can be virtually expanded to increase performance. Our results show that memory traffic can be significantly reduced without performance degradation. The proposed scheme achieves 47% reduction on memory traffic and provides 8% performance gain over the baseline system.