完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Tseng, Wang-Dauh | |
dc.contributor.author | Lin, Hsu-Yang | |
dc.date.accessioned | 2009-08-23T04:43:04Z | |
dc.date.accessioned | 2020-05-25T06:51:28Z | - |
dc.date.available | 2009-08-23T04:43:04Z | |
dc.date.available | 2020-05-25T06:51:28Z | - |
dc.date.issued | 2007-01-26T02:03:29Z | |
dc.date.submitted | 2006-12-04 | |
dc.identifier.uri | http://dspace.lib.fcu.edu.tw/handle/2377/3496 | - |
dc.description.abstract | In this paper we propose a new approach to generate multiple input control patterns for applying to the primary inputs during shift cycle such that the switching activity occurred in the combinational part of the circuit under test can be suppressed as much as possible. Experiments performed on the ISCAS 89 benchmark circuits show that the proposed approach can always produce better results than the existing approaches. | |
dc.description.sponsorship | 元智大學,中壢市 | |
dc.format.extent | 6p. | |
dc.format.extent | 3837062 bytes | |
dc.format.mimetype | application/pdf | |
dc.language.iso | zh_TW | |
dc.relation.ispartofseries | 2006 ICS會議 | |
dc.subject.other | Power-Aware Design and Test | |
dc.title | Generation of Multiple Primary Input Blocking Patterns for Power Minimization during Scan Testing | |
分類: | 2006年 ICS 國際計算機會議 |
文件中的檔案:
檔案 | 描述 | 大小 | 格式 | |
---|---|---|---|---|
ce07ics002006000045.pdf | 3.75 MB | Adobe PDF | 檢視/開啟 |
在 DSpace 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。