瀏覽 的方式： 關鍵字 Power-Aware Architecture Synthesis
顯示 1 到 4 筆資料，總共 4 筆
| 題名 | 作者 | 日期 |
| Designing A Power-aware Embedded System with Reducing Memory Access Frequencies | Chen, Ching-Wen; Ku, Chang-Jung; Weng, Chuan-Chi | 2007-01-25T06:51:06Z |
| Instruction Fetch Power Reduction Using Forward-Branch and Subroutine Bufferable Innermost Loop Buffer | Wu, I-Wei; Tein, Bin-Hua; Chung-Ping Chung | 2007-01-25T06:47:21Z |
| Next Entries Pre-activation for Low Power Drowsy BTB | Chiao, Wei-Hau; Pan, Han-Lun; Shann, Jyh-Jiun; Chung, Chung-Ping | 2007-01-25T06:52:48Z |
| Power-Aware Register Assignment for Multi-Banked Register Files | Shieh, Wann-Yun; Hsu, Shu-Yi | 2007-01-25T06:49:06Z |
