Power-Aware Register Assignment for Multi-Banked Register Files

Abstract

The multi-banked register file (MBRF) is one of the most effective approaches to resolve the complexity of the monolithic register files. In order to apply the multi-banked register file to a high-end embedded processor, we design the dynamic voltage (DVS) scaling approach for MBRF to satisfy the energy constraints. However, we found that distributed bank-access behavior prevents voltage scaling from identifying when a bank is active or not. To resolve this problem, in this paper, we analyze the access behavior of temporary-values, and change their storage in banks to increase the opportunities of power saving for infrequently-used register banks. We then turn these infrequently-used register banks into lower mode by our proposed DVS circuit. For a MBRF architecture with four banks, simulation results show that, on average, our approach reduces about 19% energy consumption while performance lose can be limitted by less than 2%, compared with the MBRF without DVS.