瀏覽 的方式： 關鍵字 Power-Aware Design and Test
顯示 1 到 4 筆資料，總共 4 筆
| 題名 | 作者 | 日期 |
| Analysis of Iterative and Simulated Annealing HW/SW Co-Synthesis Algorithms for Energy-Aware Network-on-Chip Design | Hung, Wei-Hsuan; Chen, Yi-Jung; Yang, Chia-Lin | 2007-01-26T01:54:12Z |
| Generation of Multiple Primary Input Blocking Patterns for Power Minimization during Scan Testing | Tseng, Wang-Dauh; Lin, Hsu-Yang | 2007-01-26T02:03:29Z |
| Reduction of Test Power during Test Application in Full-Scan Sequential Circuits with Multiple Capture Techniques | Lin, Hsu-Yang; Tseng, Wang-Dauh; Lai, Liang-Chien | 2007-01-26T02:02:06Z |
| Simultaneous Application of Power Management Scheduling and Operation Delay Selection for Peak Power Minimization | Yen, Wei-Ting; Cheng, Chun-Hua; Huang, Shih-Hsu | 2007-01-26T01:59:14Z |
