Instruction Decoder Implemented with Balsa for an Asynchronous Pipelined 8051 compatible Microcontroller

Abstract

The 8051 is one of the most widely used microcontrollers today especially on many simple embedded systems. Traditionally, digital systems are implemented with synchronous circuits. Because of synchronous circuit nature, a global distributed clock signal is needed. However, the global distributed clock may cause some problems, such as harder and harder clock distribution, worse-case performance, sensitive to variations in voltage and temperature, more power consumption, and higher EMI. These problems can be easily overcome by asynchronous circuits. It is widely known that the 8051 processor is the most popular 8-bit microcontroller; however, because of its CISC nature, the instruction decoder is not very easy to implement, especially for asynchronous circuits. In this paper, we propose a new instruction fetcher and decoder model for an asynchronous pipelined 8051 microcontroller. The proposed design is modeled with a CSP-based asynchronous HDL called Balsa HDL and synthesized into Xilinx netlist with the Balsa synthesis tool. In addition, the performance will be estimated with several different design configurations.