Instruction Scheduling and Register Relabeling Algorithms for Reducing Switching Activity between Instructions

Abstract

In this paper, we present instruction scheduling and register relabeling algorithms for ARM processor to reduce switching activity between instructions. Given the original assembly code and machine code produced by compiler, the proposed algorithm first builds the corresponding DAG (Directed Acyclic Graph) and DDG (Data Dependence Graph) of the assembly code. Then we reorder the sequence of instructions in DAG by our proposed list scheduling algorithm (move_ahead) and re-allocate registers into variables of DDG by tabu search to decrease the switching activity. Experimental results show that our proposed algorithms can achieve 5 % to 25% decrement in switching activity without sacrificing any program performance.