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dc.contributor.authorLu, Shyue-Kung
dc.contributor.authorChen, Ying-Mou
dc.contributor.authorLu, Mau-Jung
dc.date.accessioned2009-08-23T04:41:37Z
dc.date.accessioned2020-05-25T06:39:52Z-
dc.date.available2009-08-23T04:41:37Z
dc.date.available2020-05-25T06:39:52Z-
dc.date.issued2006-10-16T01:49:55Z
dc.date.submitted2002-12-18
dc.identifier.urihttp://dspace.lib.fcu.edu.tw/handle/2377/1346-
dc.description.abstractThis paper presents testable design and built-in self-test (BIST) schemes for digital finite impulse response (FIR) filters. According to the characteristics of the bijective cell function, pseudoexhaustive test patterns can be applied to each module in the filter and faulty effects can be propagated to the primary outputs. The test pattern generator can be implemented with a simple binary counter. We use the checksum approach for output response analysis. In order to make the filter testable, simple ad-hoc DFT modifications should be made. Our approach is also suitable for diagnosis of a faulty module. In order to verify our approach, a cellbased design of the BISTed filter has been implemented and verified. Experimental results show that 100% fault coverage is achieved. The hardware overhead is 7.12% and 5.53% for wordlength = 16 and 24, respectively.
dc.description.sponsorship東華大學,花蓮縣
dc.format.extent4p.
dc.format.extent575720 bytes
dc.format.mimetypeapplication/pdf
dc.language.isozh_TW
dc.relation.ispartofseries2002 ICS會議
dc.titleTestable Design and BIST Schemes for FIR Filter Structures
分類:2002年 ICS 國際計算機會議

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