Behavioral Synthesis-For-Testability for Conditional Statements with Multiple Branches

Abstract

As the digital design moves to higher levels of abstraction, high-level test synthesis methodologies attract many research interests. Many conditional statements in behavioral desriptions tend to produce testability problems in synthesized circuits, so it would be better if they are taken care of in the early stage of the design cycle. In this paper we present a HLTS methodology based on BIST. The presented methods transform conditional case statements in the original design to a functionally equivalent description that eliminates testability problems exist in the original design. Experimental results are provided to show the effectiveness of these methods.