An FIFO Memory Design for 8-to-32 Data Exchange Bus

Abstract

An FIFO memory architecture is proposed to be utilized in data exchange between processing units which possess non-homogeneous bus widths. Neither arbiter logics nor modules are required in such a design to determine input sequences or output sequences. Hence, the delay is drastically shortened. Two pointers, which are read pointer (RP) and write pointer (WP), respectively, point to the head and the tail of the valid data queue in the FIFO. The simulation results of the proposed design which is implemented by Verilog HDL (hardware description language) reveal that the design is capable of processing the data under a 200 MHz clock rate using TSMC 0.35 1P4M CMOS technology.