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dc.contributor.authorShiau, Yeu-Horng
dc.contributor.authorJou, Jer-Min
dc.contributor.authorWang, Tsung-Chih
dc.date.accessioned2009-08-23T04:41:07Z
dc.date.accessioned2020-05-25T06:44:53Z-
dc.date.available2009-08-23T04:41:07Z
dc.date.available2020-05-25T06:44:53Z-
dc.date.issued2006-10-23T15:33:40Z
dc.date.submitted2002-12-18
dc.identifier.urihttp://dspace.lib.fcu.edu.tw/handle/2377/2210-
dc.description.abstractThis paper presented a design method of modular scalable HMM-based continuous speech recognition / convolutional decoder IP. This IP includes three major functions: (i) Hidden Markov Model based continuous speech recognition (ii) convolutional decoder of error control coding (iii) modular scalable IP design. Since the recognition kernel of HMM-based speech recognition system and the decoding kernel of convolutional coding system are similar, we integrate the two functions in one IP by working with same hardware modules. Besides, in order to satisfy the number of recognizable words requirement of most speech recognition applications, we develop the modular scalable IP architecture that one can increase the number of recognizable words by cascoding connection with speech recognition IPs and extension modules.
dc.description.sponsorship東華大學,花蓮縣
dc.format.extent21p.
dc.format.extent367263 bytes
dc.format.mimetypeapplication/pdf
dc.language.isozh_TW
dc.relation.ispartofseries2002 ICS會議
dc.subjectSpeech recognition
dc.subjectHMM
dc.subjectConvolutional code
dc.subjectViterbi algorithm
dc.subjectModular scalable
dc.subjectIP design
dc.subject.otherMultimedia Technologies
dc.titleDesign of Modular Scalable HMM-based Continuous Speech Recognition / Convolutional Decoder IP
分類:2002年 ICS 國際計算機會議

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