Efficient VLSI Architecture Designs for Shape-Adaptive DWT and Zero Tree Coding

Abstract

In this paper, an efficient algorithm and its VLSI architecture design for a progressive still image coding system are presented. The image transform is a shape adaptive discrete wavelet transform (SA-DWT) using lifting scheme. The transformed image is then compressed by a shape adaptive zero tree coding scheme (SA-ZTC) in a progressive manner. The simulation results indicate the proposed SA-ZTC scheme enjoys a 4dB PSNR performance edge over the SPHIT algorithm under given bit rates. Combining both SA-DWT and SA-ZTC schemes, an efficient VLSI design was accomplished using the TSMC 0.35um 1P4M process. The post layout simulation results show that the chip is capable of working at above 60MHZ clock rate. The computing power implies a sustained processing rate of 42 frames/sec for 1024×1024 images.