New Modular Construction of Low-Complexity bit-parallel Systolic Multipliers for a class of Finite Fields GF(2m)

Abstract

An efficient design for low-complexity and fast computation for the bit-parallel systolic architecture is of practical concern in many digital circuit designs. This paper presents a class of novel bit-parallel systolic multiplier over the finite field GF(2m), which is generated from the irreducible all one polynomial (AOP) and equally spaced polynomial (ESP). The proposed architectures have properties of highly regularity, simplicity, and shorter latency, which are important in designing the bit-parallel systolic multipliers. Moreover, the AOP-based systolic multipliers of small fields can be used to construct all the corresponding ESP-based systolic multipliers of large fields. The latency of the AOP-based and ESP-based systolic multipliers require m+2 and m+r+1 clock cycles, respectively, which are better than others. The size complexity of the proposed multipliers is smaller than previously developed multipliers of the same class. And as for the parallel systolic multipliers, the bit-parallel structures used in this paper has shorter the computation latency