Analytical Study of Performance Evaluation for x86 Instructions to Micro-ops Decoder

Abstract

Several of the recent Intel x86/compatible microprocessor designs employ a special decoder which translates the x86 instructions into RISC-like micro-operations. The decoder consists of several translators of different complexity. Each translator can convert the x86 instructions into their corresponding micro-operations. This paper proposes an analytical method that evaluates the performance of a variety of decoder architectures.