Parallel and Pipelined VLSI Architecture Designs for Distributed Arithmetic-Based Recursive Digital Filters

Abstract

In this paper we first propose a new design technique based on Distributed Arithmetic (DA) scheme to enhance high speed recursive digital filtering. The proposed design exploits parallelism down to the bit-level and can outperform the conventional bit parallel design in both speed and hardware complexity. The scheme is further improved with the introduction of algorithm look-ahead transform and design tactics such as structure pipelining and block processing. The resultant design features an initiation interval as small as the delay for computing one data bit.