完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Fu, Guan Cheng Jr | |
dc.contributor.author | Shieh, Jong Jiann Jr | |
dc.date.accessioned | 2011-03-24T19:55:01Z | |
dc.date.accessioned | 2020-05-18T03:24:10Z | - |
dc.date.available | 2011-03-24T19:55:01Z | |
dc.date.available | 2020-05-18T03:24:10Z | - |
dc.date.issued | 2011-03-24T19:55:01Z | |
dc.date.submitted | 2009-11-27 | |
dc.identifier.uri | http://dspace.lib.fcu.edu.tw/handle/2377/30067 | - |
dc.description.abstract | Deeply pipelined architecture uses the dynamic branch predictor to enhance the performance. The dynamic branch predictor of the traditional scheme is exercised every cycle and then causes many power consumptions. For this reason, we intended to eliminate unnecessary lookups for dynamic branch predictor. In this paper, we proposed a scheme to dynamically collecting non-branch instructions between adjacent branch instructions during execution stage. We save the power by using the number we collected to filter the unnecessary lookups. Simulation results show that the dynamic branch predictor power is reduced by 63.79% and 76.58% in average for SPECint2000 and SPECfp2000 respectively with negligible performance loss. | |
dc.description.sponsorship | National Taipei University,Taipei | |
dc.format.extent | 4p. | |
dc.relation.ispartofseries | NCS 2009 | |
dc.subject | dynamic branch predictor | |
dc.subject | dynamically collecting non-branch instructions | |
dc.subject | power consumption | |
dc.subject.other | Workshop on Computer Architectures, Embedded Systems and VLSI/EDA | |
dc.title | Reducing Dynamic Branch Predictor Lookups by Dynamically Collecting Non-branch Instructions | |
分類: | 2009年 NCS 全國計算機會議 |
文件中的檔案:
檔案 | 描述 | 大小 | 格式 | |
---|---|---|---|---|
CEV 1-1.pdf | 389.26 kB | Adobe PDF | 檢視/開啟 |
在 DSpace 系統中的文件,除了特別指名其著作權條款之外,均受到著作權保護,並且保留所有的權利。