完整後設資料紀錄
DC 欄位 | 值 | 語言 |
---|---|---|
dc.contributor.author | Lee, Chih-Hung Jr | |
dc.contributor.author | Cheng, Chun-Hua Jr | |
dc.contributor.author | Huang, Shih-Hsu Jr | |
dc.date.accessioned | 2011-03-24T23:37:35Z | |
dc.date.accessioned | 2020-05-18T03:24:30Z | - |
dc.date.available | 2011-03-24T23:37:35Z | |
dc.date.available | 2020-05-18T03:24:30Z | - |
dc.date.issued | 2011-03-24T23:37:35Z | |
dc.date.submitted | 2009-11-28 | |
dc.identifier.uri | http://dspace.lib.fcu.edu.tw/handle/2377/30091 | - |
dc.description.abstract | Recent progress in manufacturing technology makes it is possible to vertically stack multiple integrated chips, to develop CAD tools according to characteristics of 3D architecture is urgent and important. In this paper, we propose an integer linear programming formulation to perform signal through-the-silicon vias (TSV) minimization in high-level synthesis of 3D ICs. Different from previous technical literatures [1] [2] that vias number is minimized with a complementary objective; our formulation directly minimizes the accurate vias number. Since vias number is determined by layer assignment result of communicating resources rather than communicating operations, experimental results promise that our formulation is more effective and accurate on via minimization than previous technical literatures. | |
dc.description.sponsorship | National Taipei University,Taipei | |
dc.format.extent | 7p. | |
dc.relation.ispartofseries | NCS 2009 | |
dc.subject.other | Workshop on Computer Architectures, Embedded Systems and VLSI/EDA | |
dc.title | Accurate TSV Minimization in High-Level Synthesis of 3D ICs Design | |
分類: | 2009年 NCS 全國計算機會議 |
文件中的檔案:
檔案 | 描述 | 大小 | 格式 | |
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CEV 5-3.pdf | 190.54 kB | Adobe PDF | 檢視/開啟 |
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