Don’t-Care Bits Filling for Capture Power Reduction

Abstract

In this paper, we propose a don’t-care-bit filling method to successfully reduce the test power dissipation during capture cycles. An induced activity function is applied on each scan cell which estimates the potential on incurring cascaded transitions in the circuit under test (CUT) and obtain an optimal order for don’t care bit filling. Results show, this method reduces switching activity in the CUT up to 40% during the capture cycles compared with random X-filling method, and outperforms LCP X-filling method. Moreover, no area and performance overhead are incurred.