題名: Optimized Design of a Floating-Point Matrix Multiplier
作者: Yang, Lan-Chau Jr
Duh, Dyi-Rong Jr
關鍵字: Matrix multiplication
floating-point number
floating-point arithmetic
merged arithmetic
partial product matrix reduction
期刊名/會議名稱: NCS 2009
摘要: Floating-point matrix multiplications are widely used in many complex scientific computations. To accelerate such enormous computing, a large number of researches are investigating a more efficient floating-point matrix multiplier. Matrix multiplication consists of many multiplications and accumulations. Both of them sum up two vectors to one in the final stage. By using a CLA could achieve the final addition. The CLA is faster than a traditional CPA in computation time. However, it still consumes much time and many hardware costs. This work proposes an efficient design of a floating-point matrix multiplier. In the process of accumulating products, we reserve the two vectors generated from multiplication arithmetic and take advantage of CSAs to accumulate products. Finally, the carry and sum vectors generated from CSAs will be summed through a CLA. Thus one result of matrix multiplication is obtained. On the other hand, this design of floating-point matrix multiplier also includes the scalable concept. The multiplier and adder are divided into two modules. According to the demands on delay and cost, a developer can make a decision and accomplish an optimized design of a floating-point matrix multiplier.
日期: 2011-03-24T23:38:48Z
分類:2009年 NCS 全國計算機會議

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