A Tree-Block Scheduling Architecture for Separable 2-D Inverse Discrete Wavelet Transform

Abstract

In this paper, an efficient VLSI architecture for the 2-D inverse discrete wavelet transform is proposed. We adopt a tree-block pipeline-scheduling scheme in it for increasing computation performance and reducing temporary buffer. The scheme divides the input data into several wavelet blocks and processes these blocks one by one, so that the size of buffer for storing temporal data is greatly reduced to only the size of one block. The scheduling also makes the data flow tight and regular to meet high speed and low complexity. In addition, the architecture is pipelined efficiently to reach higher throughput rate. Each filter is designed regularly and modularly, so it is easily scalable for different filter lengths and different levels by adding some extra modules and some control signals. We also show that hardware utilization of the two filters is 100%. Due to its low hardware cost, small storage, regularity, and high performance, the architecture can be applied to real-time applications, such as MPEG-4 and JPEG-2000.