A Low Power Flash Analog-to-Digital Converter Using Level-Detection Method

Abstract

In this paper, a new low power design method for flash Analog to Digital Converters(ADCs) is presented. As an example of 6-bit flash ADC, all comparators are divided into 8 regions. We use level-detection method to let only one region is working in every clock cycle, and then achieves the aim of low power consumption. Simulation results show that this proposed 6-bit flash ADC consumes about 37.8mW at 400Msample/s with 3.3V supply voltage in TSMC 0.35μm 2P4M process. Compared with the traditional flash ADC, our level-detection method can reduce about 69.1% in power consumption.