| 題名 | 作者 | 日期 |
| A 500MHz, 8-Stage Pipeline RISC Microprocessor Design with Sub-Computing | Hu, Ya-Lun; Chang, Ming-Ku; Chen, Tien-Fu; Shiu, Fang-Yu; Cheng, You-Hsiang | 2007-01-25T06:12:32Z |
| A New Approach for Improving Ported Java JIT Compilers for Embedded Systems | Huang, Shuai-Wei; Chen, Yu-Sheng; Yang, Wuu; Hsu, Wei-Chung; Shann, Jean Jyh-Jiun | 2009-01-19T07:41:20Z |
| A New Scheme to Reducing Data Stall with Data Prefectching Table and History Table | Wang, Lung-Hsiung; Wang, Yen-Hsin; Tu, Jih-Fu | 2006-10-18T08:11:42Z |
| A Optimal Arbiter Design for NoC | Lee, Yun-Lung; Jou, Jer Min; Chen, Yen-Yu; Wu, Sih-Sian | 2009-02-10T07:16:23Z |
| A Parallel VLSI Architecture for Two-Dimensional Discrete Periodized Wavelet Transfrom | Hung, King-Chu; Huang, Yu-Jung; Wang, Chia-Ming; Hung, Yao-Shan | 2006-10-18T07:57:09Z |
| A Study for Carry Propagation Delay of Digital Ratioed Compressors | Wang, Chua-Chin; Huang, Chenn-Jung; Lee, Po-Ming | 2006-10-18T08:35:42Z |
| A Superscalar Dual-Core Architecture for ARM ISA | Chiu, Jih-Ching; Chou, Yu-Liang; Chen, Po-Kai | 2007-01-25T06:14:11Z |
| Analysis of High-Performance Sorting Algorithms on AIX for Mainframe Operation Offload | Pattnaik, Pratap; Wu, C. Eric; Gokul, Kandiraju | 2009-01-19T07:46:05Z |
| Behavioral Synthesis-For-Testability for Conditional Statements with Multiple Branches | Yung, C.-Z.; Wang, S.-J. | 2006-10-18T08:21:18Z |
| Boundary Analysis for Buddy Systems | Dan, Chia-Tien; Srisa-an, Witawas; Chang, J.Morris | 2006-10-18T17:14:57Z |
| Conditional Diagnosability of the BC Networks under the Comparison Diagnosis Model*+ | Hsu, Guo-Huang; J. M. Tan, Jimmy | 2009-02-10T07:29:41Z |
| Coverage Evaluation for Test Programs of X86 Compatible Microprocessors | Wang, Kuochen; Liu, Sanjin | 2006-10-18T09:15:01Z |
| CPSS：An Integrated Simulator for Parallel Systems | Tao, Lixin | 2006-10-18T17:07:55Z |
| Design of A Reconfigurable Floating-Point Unit | Lee, Yun-Lung; Jou, Jer Min | 2009-02-10T07:16:08Z |
| Design of System Resource Manager of Reconfigurable Architecture | Lin, Chih-Tung; Horng, Shi-Jinn; Hwang, Chao-Jang; Hung, Yi-Shu | 2009-02-10T07:21:29Z |
| Design, Implementation and Error Analysis of Redundant CORDIC Processors for Fast Vector Rotation and Trigonometric Function Evaluation | Hsiao, Shen-Fu; Liu, Chung-Yi; Chen, Jen-Yin | 2006-10-18T09:29:21Z |
| Effective Prefetching and Replacement Policies in the Scalable Clustering-Based Multiprocessor System Design | Pean, Der-Lin; Huang, Hsuan-Woei; Wu, Jia-Rong; Chen, Cheng | 2006-10-18T17:03:38Z |
| Enhanced RAM-less Modular 2-Dimensional Pipelined FFT | Musleh, Maan; Aboelaze, Mokhtar | 2009-01-19T06:55:42Z |
| Improving Branch Target Prediction with Register References | Liu, Yueh-Hung; Chen, Chang-Jiu | 2006-10-18T08:27:15Z |
| Instruction Decoder Implemented with Balsa for an Asynchronous Pipelined 8051 compatible Microcontroller | Chen, Chang-Jiu; Cheng, Wei-Min; Wang, Tuan-Chieh; Chang, Yuan-Teng; Tsai, Hung-Yue | 2009-02-09T02:41:56Z |
