Accurate TSV Minimization in High-Level Synthesis of 3D ICs Design

Abstract

Recent progress in manufacturing technology makes it is possible to vertically stack multiple integrated chips, to develop CAD tools according to characteristics of 3D architecture is urgent and important. In this paper, we propose an integer linear programming formulation to perform signal through-the-silicon vias (TSV) minimization in high-level synthesis of 3D ICs. Different from previous technical literatures [1] [2] that vias number is minimized with a complementary objective; our formulation directly minimizes the accurate vias number. Since vias number is determined by layer assignment result of communicating resources rather than communicating operations, experimental results promise that our formulation is more effective and accurate on via minimization than previous technical literatures.